1. Field of the Invention
This invention relates generally to a method and apparatus for electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) technologies and, more particularly, to a three-dimensional (3-D) ESD SOI structure.
2. Discussion of the Related Art
Metal oxide semiconductor field effect transistor (MOSFET) scaling on bulk silicon has been the primary focus of the semiconductor and microelectronic industry for achieving complementary metal oxide semiconductor (CMOS) chip performance and density objectives. The shrinking of MOSFET dimensions for high density, low power and enhanced performance requires reduced power-supply voltages. Because power consumption (P) is a function of capacitance (C), power supply voltage (V), and transition frequency (f), in accordance with the expression P=CV.sup.2 f, the focus has been on reducing both C and V as the transition frequency f increases. As a result, dielectric thickness and channel length are scaled with power-supply voltage. Power-supply reduction continues to be the trend for future low-voltage CMOS. However, with power supply reduction, transistor performance is severely impacted by both junction capacitance and the MOSFET body effect at lower voltages. As technologies scale below 0.25-.mu.m channel lengths, to 0.15 and 0.1 .mu.m, short-channel effects (SCE) control, gate resistance, channel profiling and other barriers become an issue for advanced CMOS technologies. While significant success has been achieved with successive scaling of bulk CMOS technology, the manufacturing control issues and power consumption will become more difficult with which to deal.
Using silicon-on-insulator (SOI) substrates, many of the concerns and obstacles of bulk-silicon CMOS can be eliminated at low power supply voltages. CMOS-on-SOI has significant advantages over bulk CMOS technology and will achieve the scaling objectives of low power and high performance for future technologies. CMOS-on-SOI provides low power consumption, low leakage current, low capacitance diode structures, good sub-threshold I-V characteristics (better than 60 mV/decade), a low soft error rate from both alpha particles and cosmic rays, good static random access memory (SRAM) access times, and other technology benefits. SOI process techniques include epitaxial lateral overgrowth (ELO), lateral solid-phase epitaxy (LSPE) and full isolation by porous oxidized silicon (FIPOS) as are known in the art.
SOI has not become a mainstream CMOS technology in view of the rapid improvement in bulk CMOS technology performance, however, SOI is a contender for mainstream CMOS applications. One of the barriers to implementing SOI as a mainstream CMOS technology is the "floating body" issue. Another barrier is electrostatic discharge protection (ESD). With respect to ESD protection, one problem with SOI is that there are no diodes natural to the process that are not in the presence of a polysilicon gate edge. The primary reason this is a concern is that electrical overload of the polysilicon gate structure occurs as well as the high capacitance per unit length in the SOI MOSFET structure.
ESD protection of SOI structures has been of interest for silicon-on-sapphire (SOS) and SOI applications. In early SOS/SOI literature, SOS and SOI were regarded as costly, having low volume, and capable of exotic applications where ESD robustness was more of a curiosity than a manufacturing necessity or supplier objective. To achieve ESD robustness in a mainstream SOI technology suitable for high volume commercial usage, ESD protection structures and circuitry must have low resistance and capacitance, as well as require only a small percentage of semiconductor chip area. Disadvantages of SOI ESD networks formed solely in the SOI layer include: 1) high thermal impedance to the bulk substrate, 2) thin films, 3) polysilicon gate structures, and 4) a lack of vertical silicon diodes. A high thermal impedance creates high surface temperatures in an SOI film thereby leading to thermal secondary breakdown in SOI devices formed in the SOI film. Thin film SOI devices also lead to an existence of high current densities, thus creating significant power/density constraints. In thin film SOI devices, the polysilicon gate structures create the existence of high capacitance structures and are prone to electrical overload and dielectric breakdown. A lack of vertical structures in SOI devices prevents electrical current from being dissipated to the underlying bulk substrate and thus forces construction of wide perimeter lateral structures. As a result, negative pulse SOI ESD protection is as difficult to provide as positive pulse SOI ESD protection. In bulk silicon, using comparatively smaller structures, ESD protection for negative mode pulses is easily achieved because of current dissipation to the bulk substrate; whereas, in SOI this is not true. The latter forces designers to allocate as much active silicon chip area for negative mode ESD protection as the positive mode ESD protection schemes.
In the prior art, there are different alternatives suggested to date to achieve ESD protection. FIG. 1 is exemplary of an NMOSFET 10 including n+ source and drain regions 12, p-channel region 14, gate oxide and sidewall spacers 16, gate electrode 18, and isolation regions 20 formed over a buried oxide 22 and underlying p substrate 24, as is known in the art. It is known in the art to use standard circuits constructed in SOI for ESD protection. K. Verhaege et al. in "Analysis of Snapback in SOI NMOSFETs and its Use for an SOI ESD Protection Circuit," Proceedings of the IEEE SOI Conference, pp. 140-141, 1992, and "Double Snapback in SOI NMOSFETs and its Application for SOI ESD Protection," IEEE Electron Device Lett., Vol. 14, No. 7, July 1993, pp. 326-328, demonstrate the usage of an SOI MOSFET transistor as an ESD protection device. In U.S. Pat. No. 4,989,057, issued Jan. 29, 1991 to Lu, entitled "ESD Protection for SOI Circuits," demonstrates the usage of transistors in an SOI film for ESD protection. In another article by Voldman et al. entitled "CMOS-on-SOI ESD Protection Networks", EOS/ESD Proceedings, September 1996, it has been demonstrated that thin film SOI ESD devices can be constructed by configuring MOSFETs in diode modes of operation. One problem with thin film SOI ESD devices, however, is that SOI-based ESD circuits are worse than bulk devices by at least a factor of two (2.times.). In an article by M. Chan et al. entitled "Comparison of ESD Protection Capability of SOI and Bulk CMOS Output Buffers," IRPS 1994, it has been demonstrated that SOI circuits are 2.times. less ESD robust. To therefore attain a robustness comparable with bulk ESD protection then will require very large SOI ESD networks which will be unacceptable in size, or capacitance loading. Another problem in the art is that the known SOI ESD structures are all MOSFET based. The above mentioned SOI ESD structures all disadvantageously introduce a polysilicon gate structure. A main concern with the polysilicon gate structure is dielectric overload and high capacitance per unit width. The alternatives to SOI ESD protection, as discussed above, are unacceptable from a reliability and a functional perspective.
In other known implementations, CMOS-on-SOI structures have utilized bulk elements adjacent to the active core SOI circuitry. For example, U.S. Pat. No. 4,889,829, issued Dec. 26, 1989 to Kawai and entitled "Method for producing a semiconductor device having a silicon-on-insulator structure," discloses, referring now to FIG. 2, a method of building bulk transistors 30 in a substrate 32 and SOI transistors 34 on the insulating film 36 overlying the substrate 32 In the methodology of the '829 patent, it is required that the bulk transistor 30 be constructed adjacent to the active area structures 34 in the same plane. The method of Kawai thus disadvantageously requires additional semiconductor chip area devoted to the bulk transistors, as well as, introduces undesirable topography concerns. In other words, the method and structure taught by Kawai introduces a significantly varied topography, which would be unacceptable for high density and planarity integration applications.
Furthermore, U.S. Pat. No. 5,399,507, issued March, 1995 to Sun, entitled "Fabrication of Mixed Thin film and bulk semiconductor substrate for integrated circuit applications," discloses a mixed thin film and bulk semiconductor substrate. According to Sun, ESD devices are constructed in bulk silicon. An oxygen implant is masked for forming a buried insulating layer and core SOI devices are built over the insulating layer. In addition, ESD MOSFET structures are placed adjacent to active integrated circuits in the same physical silicon plane. While the teaching of Sun eliminates planarity concerns, it however leads to undesirable silicon dislocations, which are highly unacceptable from a manufacturing perspective. To avoid silicon dislocations, the active core SOI structures must be spatially separated to avoid yield concerns. The latter, however, introduces an area disadvantage. Whereas the proposed solutions thus far discussed solve the concern of building ESD networks in the thin SOI film, they do not resolve semiconductor manufacturing problems, yield and topography issues.
In the above discussed related art, no ESD solution has been proposed that uses ESD structures under active circuitry of a CMOS-on-SOI structure to eliminate the problem of an excessive consumption of semiconductor chip area. No three-dimensional structures are suggested or proposed as ESD solutions. Using a dual-gate MOSFET, as taught U.S. Pat. No. 4,907,053 issued Mar. 6, 1990 to in T. Ohmi, entitled "Semiconductor Integrated Circuit," the problem of back gate biasing in an SOI MOSFET transistor is addressed. T. Ohmi demonstrates that it is possible to construct a SOI MOSFET with a top gate and a bottom gate where the bottom gate is placed in the bulk and the top gate is above the SOI film. In the disclosure by T. Ohmi, the second bottom gate must be aligned directly under the channel region. The second gate is used only in a positive polarity so as to act with the utility of a back-plane to modulate the channel region of the insulator. T. Ohmi does not use the back gate for any function other than controlling the electrical potential of the back-plane. T. Ohmi, furthermore, does not demonstrate the existence of a second gate contained within a well structure. In addition, all of the above-mentioned structures introduce a polysilicon gate structure. The concern with a polysilicon gate structure is dielectric overstress, ESD, and high capacitance per unit width. The solutions, as discussed above, are unacceptable from a reliability and functional perspective.